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...cture consists of four key differentiating features that enhance the application performance of the AMD Athlon XP processor: 1. Nine-issue, superscalar, fully pipelined microarchitecture 2. Superscalar, fully pipelined floating point unit (FPU) 3. Hardware data prefetch 4. Enhanced Translation Look-aside Buffers (TLBs) Figure 1: AMD AthlonTM XP Microarchitecture Block Diagram Load / Store Queue Unit IEU AGU Instruction Control Unit (72-entry) Fetch/Decode Control 2-way, 64KB Data Cache 40-entry L1 TLB/256-entry L2 TLB 3-Way x86 Instruction Decoders FPU Register File (88-entry) FADD MMX 3DNow! FStore FMUL MMX 3DNow! IEU Integer Scheduler (18-entry) FPU Stack Map / Rename 2-way, 64KB Instruction Cache 24-entry L1 TLB/256-entry L2 TLB Predecode Cache Branch Prediction Table L2 Cache 16-way, 256KB Bus Interface Unit FPU Scheduler (36-entry) AGU IEU AGU System Interface W H I T E P A P E R Page 7 The AMD Athlon™ XP Processor February 10, 2003 QuantiSpeed™ Architecture: Nine-issue, Superscalar, Fully Pipelined Microarchitecture with High-Performance Cache Memory Architecture, and Three Full x86 Instruction Decoders At the heart of QuantiSpeed architecture is a fully pipelined, nine-issue, superscalar processor core. The AMD Athlon XP processor provides a wider execution bandwidth of nine execution pipes when compared with competitive x86 processors with up to six execution pipes. The nine execution engines are comprised of three address calculation units, three integer units, and three floating-point units. In order to supply such a highly superscalar microarchitecture, the AMD Athlon XP processor implements a very large on-chip cache architecture, particularly in the L1 caches closest to the core. The AMD Athlon XP processor’s high-performance, on-chip cache architecture includes a dual-ported 128KB split-L1 cache with separate snoop ports, and an integrated full-speed...