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4 bit binary adder subtractor

Introduction

The objective is to design a 4-bit binary adder and subtractor, which can be implemented in a Field Programmable Gate Array. ...


Design process

To create a 4-bit adder/subtractor using a hierarchy approach, the design needs to be broken down into levels. ... A 4-bit adder/subtractor comprises of 4 1-bit adder/subtractors, each of these is built from a full adder. The full adders are built from two half adders, in the lowest level the half adder is constructed from logic gates. The simplest level for this design uses logic gates to construct the half adder.

Half Adder
The half adder is built using two logic gates, one AND gate and one Exclusive OR gate. To run a computer simulation of the half adder input and output ports are added to the design. ... The half adder is tested by putting in signals, either a 0 or 1, for the two inputs A and B. The correct operation for the half adder is shown in the truth table. This half adder is then useable as a block in the next level.

Input     Output
A     B     Carry     Sum
0     0     0     0
0     1     0     1
1     0     0     1
1     1     1     0
Block diagram showing half adder.
Full Adder

The next stage is to build up a full adder. ... The full adder is not to be made from using gates, it is made by using two half adders that are now available as blocks in the computer program. Using blocks makes the design quicker to build and reduces the chance of error, as the half adder has already been built and is operating correctly. The full adder is built with two half adder blocks and one OR logic gate. A full adder has three inputs, the inputs are A and B on one half adder block and A from the second half adder block. The two carry outputs from both half adder blocks are put into OR gate, the out put from this is the carry out for the full adder. The sum of the first half adder block is connected to the B input of the second half adder; the output sum on the second half adder is the overall sum for the full adder. The full adder can be simulated, and the operation checked. For a full adder there are eight possible inputs, as shown in the truth table.


Approximate Word count = 1996
Approximate Pages = 8
(250 words per page double spaced)

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